Benchmark ADC16 Specifications

March 2008 Rev. 3 1/141ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, I2C INTERFACES

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx10/1413 REGISTER & MEMORY MAPAs shown in the Figure 4, the MCU is capable of addressing 64K bytes of mem

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx100/141OPERATING CONDITIONS (Cont’d)13.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to g

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx101/141FUNCTIONAL OPERATING CONDITIONS (Cont’d)Figure 56. High LVD Threshold Versus VDD and fOSC for ROM dev

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx102/14113.4 SUPPLY CURRENT CHARACTERISTICSThe following current consumption specified for the ST7 functional

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx103/141SUPPLY CURRENT CHARACTERISTICS (Cont’d)13.4.2 WAIT and SLOW WAIT Modes Figure 61. Typical IDD in WAIT

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx104/141SUPPLY CURRENT CHARACTERISTICS (Cont’d)13.4.3 HALT Mode 13.4.4 Supply and Clock ManagersThe previous

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx105/14113.5 CLOCK AND TIMING CHARACTERISTICSSubject to general operating conditions for VDD, fOSC, and TA.13

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx106/141CLOCK AND TIMING CHARACTERISTICS (Cont’d)13.5.3 Crystal and Ceramic Resonator OscillatorsThe ST7 inte

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx107/141CLOCK AND TIMING CHARACTERISTICS (Cont’d)13.5.3.2 Typical Ceramic ResonatorstSU(OSC) is the typical o

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx108/141CLOCK AND TIMING CHARACTERISTICS (Cont’d)Figure 65. Typical Application with Ceramic ResonatorNotes:1

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx109/141CLOCK AND TIMING CHARACTERISTICS (Cont’d)Table 22. Ceramic Resonator Frequency Correlation Factor1 No

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx11/141Table 2. Hardware Register MapAddress BlockRegister LabelRegister NameReset StatusRemarks0000h0001h000

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx110/141CLOCK CHARACTERISTICS (Cont’d)13.5.4 RC OscillatorsThe ST7 internal clock can be supplied with an RC

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx111/141CLOCK CHARACTERISTICS (Cont’d)13.5.5 Clock Security System (CSS) Figure 69. Typical Safe Oscillator

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx112/14113.6 MEMORY CHARACTERISTICSSubject to general operating conditions for VDD, fOSC, and TA unless other

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx113/14113.7 EMC CHARACTERISTICSSusceptibility tests are performed on a sample ba-sis during product characte

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx114/141EMC CHARACTERISTICS (Cont’d)13.7.2 Absolute Electrical SensitivityBased on three different tests (ESD

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx115/141EMC CHARACTERISTICS (Cont’d)13.7.2.2 Static and Dynamic Latch-Up LU: 3 complementary static tests ar

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx116/141EMC CHARACTERISTICS (Cont’d)13.7.3 ESD Pin Protection StrategyTo protect an integrated circuit agains

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx117/141EMC CHARACTERISTICS (Cont’d)True Open Drain Pin ProtectionThe centralized protection (4) is not invol

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx118/14113.8 I/O PORT PIN CHARACTERISTICS13.8.1 General CharacteristicsSubject to general operating condition

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx119/141I/O PORT PIN CHARACTERISTICS (Cont’d)13.8.2 Output Driving Current Subject to general operating condi

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx12/141Legend: x=undefined, R/W=read/writeNotes:1. The contents of the I/O port DR registers are readable onl

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx120/141I/O PORT PIN CHARACTERISTICS (Cont’d)Figure 83. Typical VOL vs. VDD (standard I/Os)Figure 84. Typical

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx121/14113.9 CONTROL PIN CHARACTERISTICS13.9.1 Asynchronous RESET PinSubject to general operating conditions

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx122/141CONTROL PIN CHARACTERISTICS (Cont’d)Figure 87. Typical ION vs. VDD with VIN=VSSFigure 88. Typical VOL

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx123/141CONTROL PIN CHARACTERISTICS (Cont’d)13.9.2 ISPSEL PinSubject to general operating conditions for VDD,

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx124/14113.10 TIMER PERIPHERAL CHARACTERISTICSSubject to general operating conditions for VDD, fOSC, and TA u

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx125/14113.11 COMMUNICATION INTERFACE CHARACTERISTICS13.11.1 SPI - Serial Peripheral InterfaceSubject to gene

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx126/141COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)Figure 92. SPI Slave Timing Diagram with CPHA=11)Figu

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx127/141COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)13.11.2 I2C - Inter IC Control InterfaceSubject to ge

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx128/14113.12 8-BIT ADC CHARACTERISTICSSubject to general operating conditions for VDD, fOSC, and TA unless o

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx129/1418-BIT ADC CHARACTERISTICS (Cont’d)ADC Accuracy Figure 96. ADC Accuracy CharacteristicsNotes:1. ADC Ac

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx13/1414 FLASH PROGRAM MEMORY4.1 INTRODUCTIONFLASH devices have a single voltage non-volatile FLASH memory th

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx130/14114 PACKAGE CHARACTERISTICS14.1 PACKAGE MECHANICAL DATA Figure 97. 32-Pin Shrink Plastic Dual In Line

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx131/14114.2 THERMAL CHARACTERISTICS Notes:1. The power dissipation is obtained from the formula PD=PINT+PPO

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx132/14114.3 SOLDERING INFORMATIONIn order to meet environmental requirements, ST offers these devices in ECO

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx133/14115 DEVICE CONFIGURATION AND ORDERING INFORMATIONEach device is available for production in user pro-g

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx134/14115.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODECustomer code is made up of the ROM con

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx135/141TRANSFER OF CUSTOMER CODE (Cont’d) MICROCONTROLLER OPTION LISTCustomer . . . . . . . . . . . . . . .

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx136/14115.3 DEVELOPMENT TOOLSSTmicroelectronics offers a range of hardware and software development tools fo

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx137/141DEVELOPMENT TOOLS (Cont’d)15.3.1 PACKAGE/SOCKET FOOTPRINT PROPOSALTable 28. Suggested List of SDIP32

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx138/14115.4 ST7 APPLICATION NOTES IDENTIFICATION DESCRIPTIONEXAMPLE DRIVERSAN 969 SCI COMMUNICATION BETWEEN

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx139/141AN 982 USING ST7 WITH CERAMIC RESONATORAN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTIONAN1015 SOFTWAR

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx14/1415 CENTRAL PROCESSING UNIT5.1 INTRODUCTIONThis CPU has a full 8-bit architecture and contains six inter

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx140/14116 SUMMARY OF CHANGESDescription of the changes between the current release of the specification and

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx141/141Please Read Carefully:Information in this document is provided solely in connection with ST products.

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx15/141CPU REGISTERS (cont’d)CONDITION CODE REGISTER (CC) Read/WriteReset Value: 111x1xxxThe 8-bit Condition

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx16/141CENTRAL PROCESSING UNIT (Cont’d)Stack Pointer (SP)Read/WriteReset Value: 01 7FhThe Stack Pointer is a

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx17/1416 SUPPLY, RESET AND CLOCK MANAGEMENTThe ST72104G, ST72215G, ST72216G and ST72254G microcontrollers inc

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx18/1416.1 LOW VOLTAGE DETECTOR (LVD)To allow the integration of power management features in the application

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx19/1416.2 RESET SEQUENCE MANAGER (RSM)6.2.1 IntroductionThe reset sequence manager includes three RE-SET sou

Table of Contents1412/14121 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx20/141RESET SEQUENCE MANAGER (Cont’d)6.2.2 Asynchronous External RESET pinThe RESET pin is both an input and

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx21/1416.3 MULTI-OSCILLATOR (MO)The main clock of the ST7 can be generated by four different source types com

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx22/1416.4 CLOCK SECURITY SYSTEM (CSS)The Clock Security System (CSS) protects the ST7 against main clock pro

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx23/1416.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR)Read / WriteReset Value: 000x 000x (XXh) Bit 7:5

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx24/1416.6 MAIN CLOCK CONTROLLER (MCC)The Main Clock Controller (MCC) supplies the clock for the ST7 CPU and

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx25/1417 INTERRUPTSThe ST7 core may be interrupted by one of two dif-ferent methods: maskable hardware interr

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx26/141INTERRUPTS (Cont’d)Figure 15. Interrupt Processing FlowchartTable 5. Interrupt Mapping Note1. Configur

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx27/1418 POWER SAVING MODES8.1 INTRODUCTIONTo give a large measure of flexibility to the applica-tion in term

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx28/141POWER SAVING MODES (Cont’d)8.3 WAIT MODEWAIT mode places the MCU in a low power con-sumption mode by s

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx29/141POWER SAVING MODES (Cont’d)8.4 HALT MODEThe HALT mode is the lowest power consumption mode of the MCU.

Table of Contents3/14139.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349.5

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx30/1419 I/O PORTS9.1 INTRODUCTIONThe I/O ports offer different functional modes:– transfer of data through d

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx31/141I/O PORTS (Cont’d)Figure 21. I/O Port General Block DiagramTable 6. I/O Port Mode OptionsLegend: NI -

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx32/141I/O PORTS (Cont’d)Table 7. I/O Port Configurations Notes:1. When the I/O port is in input configuratio

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx33/141I/O PORTS (Cont’d)CAUTION: The alternate function must not be ac-tivated as long as the pin is configu

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx34/141I/O PORTS (Cont’d)9.4 LOW POWER MODES 9.5 INTERRUPTSThe external interrupt event generates an interrup

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx35/141I/O PORTS (Cont’d)Table 9. I/O Port Register Map and Reset ValuesAddress(Hex.)Register Label7 6 5 4 3

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx36/14110 MISCELLANEOUS REGISTERSThe miscellaneous registers allow control over several different features su

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx37/141MISCELLANEOUS REGISTERS (Cont’d)10.3 MISCELLANEOUS REGISTER DESCRIPTIONMISCELLANEOUS REGISTER 1 (MISCR

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx38/141MISCELLANEOUS REGISTERS (Cont’d)MISCELLANEOUS REGISTER 2 (MISCR2)Read / WriteReset Value: 0000 0000 (0

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx39/14111 ON-CHIP PERIPHERALS11.1 WATCHDOG TIMER (WDG)11.1.1 IntroductionThe Watchdog timer is used to detect

Table of Contents1414/14112 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx40/141WATCHDOG TIMER (Cont’d)Table 11. Watchdog Timing (fCPU = 8 MHz)Notes: Following a reset, the watchdog

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx41/141WATCHDOG TIMER (Cont’d)Table 12. Watchdog Timer Register Map and Reset Values Address(Hex.)Register La

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx42/14111.2 16-BIT TIMER11.2.1 IntroductionThe timer consists of a 16-bit free-running counter driven by a pr

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx43/14116-BIT TIMER (Cont’d)Figure 26. Timer Block DiagramMCU-PERIPHERAL INTERFACECOUNTERALTERNATEOUTPUTCOMPA

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx44/14116-BIT TIMER (Cont’d)16-bit Read Sequence: (from either the Counter Register or the Alternate Counter

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx45/14116-BIT TIMER (Cont’d)Figure 27. Counter Timing Diagram, internal clock divided by 2Figure 28. Counter

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx46/14116-BIT TIMER (Cont’d)11.2.3.3 Input CaptureIn this section, the index, i, may be 1 or 2 because there

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx47/14116-BIT TIMER (Cont’d)Figure 30. Input Capture Block DiagramFigure 31. Input Capture Timing DiagramICIE

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx48/14116-BIT TIMER (Cont’d)11.2.3.4 Output Compare In this section, the index, i, may be 1 or 2 because ther

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx49/14116-BIT TIMER (Cont’d)Notes:1. After a processor write cycle to the OCiHR reg-ister, the output compare

Table of Contents5/14113.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12113.9.2 ISPS

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx50/14116-BIT TIMER (Cont’d)Figure 33. Output Compare Timing Diagram, fTIMER = fCPU/2Figure 34. Output Compar

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx51/14116-BIT TIMER (Cont’d)11.2.3.5 One Pulse ModeOne Pulse mode enables the generation of a pulse when an e

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx52/14116-BIT TIMER (Cont’d)Figure 35. One Pulse Mode Timing ExampleFigure 36. Pulse Width Modulation Mode Ti

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx53/14116-BIT TIMER (Cont’d)11.2.3.6 Pulse Width Modulation ModePulse Width Modulation (PWM) mode enables the

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx54/14116-BIT TIMER (Cont’d)11.2.4 Low Power Modes 11.2.5 Interrupts Note: The 16-bit Timer interrupt events

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx55/14116-BIT TIMER (Cont’d)11.2.7 Register DescriptionEach Timer is associated with three control and status

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx56/14116-BIT TIMER (Cont’d)CONTROL REGISTER 2 (CR2)Read/WriteReset Value: 0000 0000 (00h)Bit 7 = OC1E Output

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx57/14116-BIT TIMER (Cont’d)STATUS REGISTER (SR)Read OnlyReset Value: 0000 0000 (00h)The three least signific

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx58/14116-BIT TIMER (Cont’d)OUTPUT COMPARE 2 HIGH REGISTER (OC2HR)Read/Write Reset Value: 1000 0000 (80h)This

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx59/14116-BIT TIMER (Cont’d)Table 14. 16-Bit Timer Register Map and Reset Values Address(Hex.)Register Label7

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx6/1411 INTRODUCTIONThe ST72104G, ST72215G, ST72216G and ST72254G devices are members of the ST7 mi-crocontro

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx60/14111.3 SERIAL PERIPHERAL INTERFACE (SPI)11.3.1 Introduction The Serial Peripheral Interface (SPI) allows

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx61/141SERIAL PERIPHERAL INTERFACE (Cont’d)Figure 38. Serial Peripheral Interface Block Diagram DR Read Buffe

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx62/141SERIAL PERIPHERAL INTERFACE (Cont’d)11.3.4 Functional DescriptionFigure 1 shows the serial peripheral

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx63/141SERIAL PERIPHERAL INTERFACE (Cont’d)11.3.4.2 Slave ConfigurationIn slave configuration, the serial clo

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx64/141SERIAL PERIPHERAL INTERFACE (Cont’d)11.3.4.3 Data Transfer FormatDuring an SPI transfer, data is simul

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx65/141SERIAL PERIPHERAL INTERFACE (Cont’d)Figure 40. Data Clock Timing DiagramCPOL = 1)CPOL = 0)MISO(from ma

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx66/141SERIAL PERIPHERAL INTERFACE (Cont’d)11.3.4.4 Write Collision ErrorA write collision occurs when the so

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx67/141SERIAL PERIPHERAL INTERFACE (Cont’d)11.3.4.5 Master Mode FaultMaster mode fault occurs when the master

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx68/141SERIAL PERIPHERAL INTERFACE (Cont’d)11.3.4.7 Single Master and Multimaster ConfigurationsThere are two

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx69/141SERIAL PERIPHERAL INTERFACE (Cont’d)11.3.5 Low Power Modes11.3.6 Interrupts Note: The SPI interrupt ev

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx7/1412 PIN DESCRIPTION Figure 2. 28-Pin SO Package PinoutFigure 3. 32-Pin SDIP Package Pinout151617181920282

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx70/141SERIAL PERIPHERAL INTERFACE (Cont’d)11.3.7 Register DescriptionCONTROL REGISTER (CR)Read/WriteReset Va

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx71/141SERIAL PERIPHERAL INTERFACE (Cont’d)STATUS REGISTER (SR)Read OnlyReset Value: 0000 0000 (00h)Bit 7 = S

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx72/141SERIAL PERIPHERAL INTERFACE (Cont’d)Table 16. SPI Register Map and Reset Values Address(Hex.)Register

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx73/14111.4 I2C BUS INTERFACE (I2C)11.4.1 IntroductionThe I2C Bus Interface serves as an interface be-tween t

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx74/141I2C BUS INTERFACE (Cont’d)Acknowledge may be enabled and disabled by software.The I2C interface addres

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx75/141I2C BUS INTERFACE (Cont’d)11.4.4 Functional DescriptionRefer to the CR, SR1 and SR2 registers in Secti

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx76/141to correctly handle a second interrupt during the 9th pulse of a transmitted byte.Note: In both cases,

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx77/141I2C BUS INTERFACE (Cont’d)Master TransmitterFollowing the address transmission and after SR1 register

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx78/141I2C BUS INTERFACE (Cont’d)Figure 45. Transfer SequencingLegend: S=Start, Sr = Repeated Start, P=Stop,

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx79/141I2C BUS INTERFACE (Cont’d)11.4.5 Low Power Modes11.4.6 InterruptsFigure 46. Event Flags and Interrupt

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx8/141PIN DESCRIPTION (Cont’d)For external pin connection guidelines, refer to Section 13 "ELECTRICAL CH

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx80/141I2C BUS INTERFACE (Cont’d)11.4.7 Register DescriptionI2C CONTROL REGISTER (CR) Read / Write Reset Valu

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx81/141I2C BUS INTERFACE (Cont’d)I2C STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h)Bit 7 = EV

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx82/141I2C BUS INTERFACE (Cont’d)Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interf

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx83/141I2C BUS INTERFACE (Cont’d)I2C CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h)Bi

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx84/141I2C BUS INTERFACE (Cont’d)I2C OWN ADDRESS REGISTER (OAR1) Read / Write Reset Value: 0000 0000 (00h)7-b

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx85/141I²C BUS INTERFACE (Cont’d)Table 17. I2C Register Map and Reset Values Address(Hex.)Register Label7 6

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx86/14111.5 8-BIT A/D CONVERTER (ADC)11.5.1 IntroductionThe on-chip Analog to Digital Converter (ADC) pe-riph

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx87/1418-BIT A/D CONVERTER (ADC) (Cont’d)11.5.3.2 Digital A/D Conversion ResultThe conversion is monotonic, m

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx88/1418-BIT A/D CONVERTER (ADC) (Cont’d)11.5.6 Register DescriptionCONTROL/STATUS REGISTER (CSR)Read / Write

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx89/1418-BIT A/D CONVERTER (ADC) (Cont’d)Table 18. ADC Register Map and Reset Values Address(Hex.)Register La

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx9/141Notes:1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx90/14112 INSTRUCTION SET 12.1 ST7 ADDRESSING MODESThe ST7 Core features 17 different addressing modes which

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx91/141ST7 ADDRESSING MODES (Cont’d)12.1.1 InherentAll Inherent instructions consist of a single byte. The op

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx92/141ST7 ADDRESSING MODES (Cont’d)12.1.6 Indirect Indexed (Short, Long)This is a combination of indirect an

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx93/14112.2 INSTRUCTION GROUPSThe ST 7 family devices use an Instruction Set consisting of 63 instructions. T

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx94/141INSTRUCTION GROUPS (Cont’d)Mnemo Description Function/Example Dst Src H I N Z CADC Add with Carry A =

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx95/141INSTRUCTION GROUPS (Cont’d)Mnemo Description Function/Example Dst Src H I N Z CJRULE Jump if (C + Z =

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx96/14113 ELECTRICAL CHARACTERISTICS13.1 PARAMETER CONDITIONSUnless otherwise specified, all voltages are re-

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx97/14113.2 ABSOLUTE MAXIMUM RATINGSStresses above those listed as “absolute maxi-mum ratings” may cause perm

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx98/14113.3 OPERATING CONDITIONS13.3.1 General Operating Conditions Figure 51. fOSC Maximum Operating Frequen

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx99/141OPERATING CONDITIONS (Cont’d)Figure 52. fOSC Maximum Operating Frequency Versus VDD Supply Voltage for